memory

Block Ram in Verilog with Vivado

Block Ram in Verilog with Vivado

You want to use Block Ram in Verilog with Vivado

There are two types of internal memory available on a typical FPGA:

  • Distributed Ram: made from the FPGA logic (LUTs)
  • Block Ram: dedicated memory blocks within the FPGA; also known as bram

However, persuading Vivado to make use of block ram isn't simple a case of changing a preference. You need to create a Verilog implementation that Vivado can infer as block ram. This recipe looks at inferring block ram on Xilinx 7 Series FPGAs (Spartan-7. Artix-7, Kintex-7, and Virtex-7), but this information should be relevant to other developers too. 

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Initialize Memory in Verilog

Initialize Memory in Verilog

You want to initialize memory from a file using Verilog.

It's common for a simulation or firmware to need data loading into a memory array. Fortunately Verilog provides the $readmemh and $readmemb functions for this very purposes. Unfortunately there is a dearth of good Verilog documentation online, so using them can be harder than it should be. This article explains the syntax and provides plenty of examples, including how to do this in Xilinx Vivado.

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