Maths

Shifting Verilog Values for CORDIC and Division

Shifting Verilog Values for CORDIC and Division

Newton-Raphson division and CORDIC methods only work in a small domain. For example, Newton-Raphson division implementations usually expect the divisor to be in the range 0.5 to 1.0. For a large number of bits this requires many single shifts and comparisons. Instead we can create a priority encoder with casex to determine the most significant bit (MSB) and then apply a single shift as required.

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Fixed Point Numbers in Verilog

Fixed Point Numbers in Verilog

Sometimes you need more precision than integers can provide, but floating point is hard (try reading IEEE 754). You could use a library or IP block, but simple fixed point maths can often get the job done with little effort. Furthermore, most FPGAs have dedicated DSP blocks that make multiplication and addition of integers really fast; we can take advantage of that with a fixed point approach.

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