Cookbook

Shifting Verilog Values for CORDIC and Division

Shifting Verilog Values for CORDIC and Division

Newton-Raphson division and CORDIC methods only work in a small domain. For example, Newton-Raphson division implementations usually expect the divisor to be in the range 0.5 to 1.0. For a large number of bits this requires many single shifts and comparisons. Instead we can create a priority encoder with casex to determine the most significant bit (MSB) and then apply a single shift as required.

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Fixed Point Numbers in Verilog

Fixed Point Numbers in Verilog

Sometimes you need more precision than integers can provide, but floating point is hard (try reading IEEE 754). You could use a library or IP block, but simple fixed point maths can often get the job done with little effort. Furthermore, most FPGAs have dedicated DSP blocks that make multiplication and addition of integers really fast; we can take advantage of that with a fixed point approach.

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Video Timings: VGA, SVGA, 720P, 1080P

Video Timings: VGA, SVGA, 720P, 1080P

You Need Video Timings

To work with standard monitors and TVs you need to use the correct video timings. This recipe includes the timings for four common modes using analogue VGA, DVI or HDMI: 640x480, 1280x720, and 1920x1080 all at 60 Hz.

Video Signals in Brief
Video signals have two phases: drawing pixels and the blanking interval. The sync signals occur within blanking intervals; separated from pixel drawing by the front porch and back porch. Horizontal sync demarcates a line and vertical sync a frame. The following diagram illustrates the different parts of the display signal for 640x480 at 60Hz; the HD resolutions work in a similar way.

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Block Ram in Verilog with Vivado

Block Ram in Verilog with Vivado

You want to use Block Ram in Verilog with Vivado

There are two types of internal memory available on a typical FPGA:

  • Distributed Ram: made from the FPGA logic (LUTs)
  • Block Ram: dedicated memory blocks within the FPGA; also known as bram

However, persuading Vivado to make use of block ram isn't simple a case of changing a preference. You need to create a Verilog implementation that Vivado can infer as block ram. This recipe looks at inferring block ram on Xilinx 7 Series FPGAs (Spartan-7. Artix-7, Kintex-7, and Virtex-7), but this information should be relevant to other developers too. 

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Initialize Memory in Verilog

Initialize Memory in Verilog

You want to initialize memory from a file using Verilog.

It's common for a simulation or firmware to need data loading into a memory array. Fortunately Verilog provides the $readmemh and $readmemb functions for this very purposes. Unfortunately there is a dearth of good Verilog documentation online, so using them can be harder than it should be. This article explains the syntax and provides plenty of examples, including how to do this in Xilinx Vivado.

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